Phase-locked loop ("PLL") circuits have been used for many years and are electronic circuits for locking an oscillator in phase with a reference signal. PLL circuits are often utilized within receivers in digital communication systems for the purpose of generating a local clock signal which is phase aligned with an incoming reference signal. The phase aligned local clock signal facilitates the receipt and processing of synchronous data sent by a transmitter in the communication system.
A conventional PLL circuit comprises a phase detector, a filter and a voltage-controlled oscillator ("VCO"). In the conventional PLL circuit, the phase detector compares the incoming reference signal and the output of the VCO. The phase detector generates an error signal that is representative of the phase difference of the reference signal and the VCO output. The error signal is filtered and applied to the control input of the VCO to produce an output signal that tracks the phase of the reference signal.
A potential problem exists for a PLL circuit used for the generation of a local clock signal for the synchronous reading of transmitted data, when the incoming reference signal is lost or interrupted. The output frequency of the VCO may drift during the absence of the reference signal, potentially causing a receiver to read the received data out of synchronization.
One prior art technique to maintain a constant phase-locked local clock signal relies on the use of multiple reference signals of the same frequency. In a circuit according to this technique, a multiplexer connects one of the multiple reference signals to an input of a PLL circuit. Sensing circuitry is used to detect any interruption of this reference signal. Upon detecting an interruption of the reference signal, the sensing circuitry causes the multiplexer to switch to a different reference signal. U.S. Pat. No. 4,972,442 to Steierman, issued on Nov. 20, 1990, describes such a prior art system which utilizes a microprocessor to switch over to the different reference signal.
A disadvantage of U.S. Pat. No. 4,972,442 and other prior art multiple reference PLLs is the lack of circuitry or other means to minimize the undesirable effects to circuit performance caused by a sudden phase difference between reference signals applied to the input of the PLL circuit before and after a switch over. For example, if the sudden shift in phase were sufficiently large, the PLL circuit may lose its phase lock, or be otherwise adversely affected, to cause the receiver to misread one or more of the incoming bits of information. As a result, the receiver would read data out of synchronization.
One measure of the effects on circuit performance caused by a sudden phase change at the PLL circuit input is time interval error ("TIE"). TIE is defined as the variation of the time delay of the generated phase-locked signal with respect to the reference signal at the input of the PLL circuit over a period of time. The TIE over a period of S seconds is defined to be the magnitude of the difference between the time delay values measured at the end and at the beginning of this period, i.e., TIE(S)=.vertline..DELTA.T(t+S)-.DELTA.T(t).vertline., where TIE(S) is the time interval error over time S and .DELTA.T(t) is the time delay at time t.
If a first reference signal and a second reference signal are in phase alignment, the TIE of the PLL output signal after switch over from the first reference signal to the second will be zero. In the alternative, if a phase variation exists between the first and second reference signals, then a TIE of a particular magnitude will occur for a time period between switch over and a point in time when the PLL circuit output signal has settled down and phase-locked on the second reference signal.
A phase difference of .pi. radians between the first and second reference signals represents a worst case condition for prior art PLL circuits. There is a substantial likelihood that a prior art PLL circuit could not track such a drastic instantaneous phase difference and as a result would lose its phase lock and enter a frequency runaway condition.
In the alternative, if the PLL circuit which generated a phase-locked signal based on a 64 KHz reference signal, did not lose its lock, a TIE of 7812.5 ns or a phase variation corresponding to one-half of a cycle would exist for the time period that the output signal is out of phase with the second reference signal by .pi. radians. The International Telegraph and Telephone Consultative Committee (CCITT) has a proposed recommendation that any TIE generated by a PLL circuit used to generate reference timing signals in a communication system should not be greater than 1000 ns for a time period of 15 seconds or longer.
It is desirable to have a multiple reference signal PLL circuit that will produce minimal TIE at a switching of reference signals. Further, it is desirable that such a circuit be of minimal complexity and constructed of inexpensive components.